Makefiles are used to automatically compile and build a program.

They consist of four sections:

  • Definitions (This is optional, this is where you put in (what's basically) #defines).
  • Target: (The name of object you’re making, (e.g. a.out). There can be multiple of these)
  • Dependencies (The files it depends on)
  • Commands (To execute. Preceded by a tab).


CC = gcc
CF = -Wall -Werror

hello: hello.c
    gcc –Wall –Werror –o hello hello.c

runbeth: beth.c beth.h
    $(CC) $(CF) –o $@ $^

all: hello